Version 11.3.0
General information on portability

Supported CPU architectures

The supported list of CPU target architectures may be found by inspecting the WT_ARCH variable present in the cmake configuration. Note that the loongarch64 platform is community-supported.

POSIX compliance

WiredTiger aims to be generally portable to any 64-bit system supporting the ANSI C11 and POSIX 1003.1 standards. Unfortunately, the real world is a little messier than the standards dictate, so WiredTiger may not compile (or work correctly) on every POSIX platform.

If WiredTiger does fail to compile (or work correctly) on your platform, we welcome either a bug report or a pull request.

Testing

To see a list of the CPU and operating system combinations WiredTiger is currently tested on, please visit our test results page. This list is determined by the availability of suitable machines. The lack of an operating system or CPU architecture on this page does not make it unsupported.

Hardware requirements of WiredTiger

Atomic reads and writes

WiredTiger requires that pointers (void *) and variables that are 8, 16, 32 and 64 bits to be read/written to atomically. For example if the first 8 bits of a 32 bit write took place and then separately the remaining 24 bits were written, another thread of control could read the memory location after the first 8 bits were written but before the subsequent 24 bits, seeing an invalid state. If two threads of control attempt to write to the same location simultaneously, the result must be one of the two values, not some combination of the both.

No Aggregated Writes of Adjacent Memory Locations

To reduce memory requirements, WiredTiger may use a 32-bit type on 64-bit machines, which is OK if the compiler doesn't turn a 32-bit load/store into a 64-bit load/store, where the 64 bits consists of two adjacent 32-bit locations.

Violating this can lead to races when two threads are cooperating. Suppose there is a thread X that finds the variable A of 32-bits set to 0 and writes in a new value. Concurrently another thread Y reads the adjacent variable B of 32-bits that are non-zero, does some operation, resets the memory location to 0. If thread X were to read the 64-bits consisting of the variable A and the adjacent variable B together, and write them both, the two threads could race.

Writes Across Cache Lines

WiredTiger doesn't depend on writes across cache lines being atomic and it ensures that a single write that is smaller or equal to 4 bytes long is never split across the cache lines. This is achieved through address alignment: we know of no architectures with cache lines other than a multiple of 4 bytes in size, therefore, aligned 4-byte accesses will always be in a single cache line.